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| 1 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc 128m [x8/x16] single 3v page mode mtp memory features ? 3.0v to 3.6v operation voltage block structure - 128 x 128kbyte erase blocks fast random / page mode access time - 120/25 ns read access time (page depth:4-word) 32-byte write buffer - 6 us/byte effective programming time performance low power dissipation - typical 15ma active current for page mode read - 80ua/(max.) standby current high performance - block erase time: 2s typ. - byte programming time: 210us typ. - block programming time: 0.8s typ. (using write to buffer command) program/erase endurance cycles: 10 cycles packaging - 44-lead sop technology - nbit (0.25u) mtp technology general description the mxic's mx26l12811mc series mtp use the most advance 2 bits/cell nbit technology, double the storage capacity of memory cell. the device provide the high density mtp memory solution with reliable performance and most cost-effective. the device organized as by 8 bits or by 16 bits of output bus. the device is packaged in 44-lead sop. it is de- signed to be reprogrammed and erased in system or in standard eprom programmers. the device offers fast access time and allowing opera- tion of high-speed microprocessors without wait states. the device augment eprom functionality with in-circuit electrical erasure and programming. the device uses a command register to manage this functionality. the mxic's nbit technology reliably stores memory con- tents even after the specific erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's charac- ter to trap or release charges from ono layer. the device uses a 3.0v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algo- rithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v.
2 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc pin configuration 44-sop (for word mode only) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a21 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce we oe q0 q8 q1 q9 q2 q10 q3 q11 a20 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 a22 gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc mx26l12811 symbol pin name a0~a22 address input q0~q15 data inputs/outputs ce chip enable input we write enable input oe output enable input vcc device power supply gnd device ground pin description 3 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mtp array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a-1~a22 ce oe we 4 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 1. block architecture mtp memory reads erases and writes in-system via the local cpu. all bus cycles to or from the mtp memory conform to standard microprocessor bus cycles. 01ffff 010000 00ffff 000000 64-kword block . . . 1 1fffff 1f0000 64-kword block 31 . . . 3fffff 3f0000 64-kword block 63 64-kword block word mode (x16) 03ffff 020000 01ffff 000000 . . . 3fffff 3e0000 . . . 7fffff a22~a-1 a22~a0 7e0000 ffffff fe0000 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block byte mode (x8) 0 1 31 63 . . . 7fffff 7f0000 64-kword block . . . 128-kbyte block 127 127 0 128 mbit 5 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc notes: 1. oe and we should never be enabled simultaneously. 2. dq refers to q0-q7 if byte is low and q0-q15 if byte is high. 3. x can be vil or vih for control and address pins. 4. see section , "read identifier codes" for read identifier code data. 5. see section , "read query mode command" for read query data. 6. command writes involving block erase, program, or lock-bit configuration are reliably executed when vcc is within specification. 7. refer to table 2 on page 7 for valid din during a write operation. table 1. bus operations command read output standby read id read read read write sequence array disable query status status (wsm off) (wsm on) notes 3 6,7 ce enabled enabled disabled enabled enabled enabled enabled enabled oe (1) vil vih x vil vil vil vil vih we (1) vih vih x vih vih vih vih vil address x x x see see x x x figure 2 table 6 q (2) data out high z high z note 4 note 5 data out q7=data out data in q15-8=high z q6-0=high z 6 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc function the device includes on-chip program/erase control cir- cuitry. the write state machine (wsm) controls block erase and word/page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register in- dicates the status of the wsm and when the wsm suc- cessfully completes the desired program or block erase operation. read the device has three read modes, which accesses to the memory array, the device identifier or the status register. the appropriate read command are required to be written to the cui. upon initial device powerup or af- ter exit from powerdown, the device automatically re- sets to read array mode. in the read array mode, low level input to ce and oe, high level input to we and address signals to the address inputs (a22-a-1) output the data of the addressed location to the data input/out- put (q15~q0). when reading information in read array mode, the de- vice defaults to asynchronous page mode. in this state, data is internally read and stored in a high-speed page buffer. a2:0 addresses data in the page buffer. the page size is 4 words or 8 bytes. asynchronous word/byte mode is supported with no additional commands required. write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. the cui is written when the device is enable, we is active and oe is at high level. address and data are latched on the earlier rising edge of we and ce. standard micro-processor write timings are used. output disable when oe is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. standby when ce disable the device (see table1) and place it in standby mode. the power consumption of this device is reduced. data input/output are in a high-impedance(high- z) state. if the memory is deselected during block erase, program or lock-bit configuration, the internal control cir- cuits remain active and the device consume normal ac- tive power until the operation completes. 7 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc command definitions device operations are selected by writing specific address and data sequences into the cui. table 2 defines the valid register command sequences. table 2. command definitions command read read read read clear write to sequence array id query status status buffer register register notes 5 6 7,8,9 bus write cycles req'd 1 > 2 > 2 2 1 > 2 first bus operation(2) write write write write write write write cycles address(3) x x x x x ba data(4,5) ffh 90h 98h 70h 50h e8h second bus operation(2) read read read write read query address(3) ia qa x ba data(4,5) id qd srd n command word sector configur- set sector clear sequence program erase ation lock-bit sector lock-bit notes 10,11 9,10 12 bus write cycles req'd 2 2 2 2 2 first bus operation(2) write write write write write write cycle address(3) x ba x x x data(4,5) 40h/10h 20h b8h 60h 60h second bus operation(2) write write write write write write cycle address(3) pa pa x ba x data(4,5) pd d0h cc 01h d0h 8 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc notes: 1. bus operations are defined in table 1. 2. x = any valid address within the device. ba = address within the block. ia = identifier code address: see figure 2 and table 13. qa = query database address. pa = address of memory location to be programmed. rcd = data to be written to the read configuration register. this data is presented to the device on a15~a0 ; all other address inputs are ignored. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 14 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we. cc = configuration code. 4. the upper byte of the data bus (q8-q15) during command writes is a "don't care" in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device and block lock codes. see section 4.3 for read identifier code data. 6. if the wsm is running, only q7 is valid; q15-q8 and q6-q0 float, which places them in a high impedance state. 7. after the write to buffer command is issued check the xsr to make sure a buffer is available for writing. 8. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode are n = 0000h to n =000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see figure 4. "write to buffer flowchart" for additional information. 9. the write to buffer or erase operation does not begin until a confirm command (d0h) is issued. 10.attempts to issue a block erase or program to a locked block. 11.either 40h or 10h are recognized by the wsm as the byte/word program setup. 12.the clear block lock-bits operation simultaneously clears all block lock-bits. 9 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 2. device identifier code memory map note: 1. a-1 is not used in either x8 or x16 mode when obtaining these identifier codes. data is always given on the low byte in x16 mode (upper byte contains 00h). 3fffff 3f0003 3f0002 3f0000 3effff block 63 reserved for future implementation reserved for future implementation (block 32 through 62) block 63 lock configuration 7fffff word address 7f0003 7f0002 7f0000 7effff block 127 reserved for future implementation reserved for future implementation (block 64 through 126) block 127 lock configuration 1f0003 1f0002 1f0000 1effff 01ffff block 31 reserved for future implementation reserved for future implementation (block 2 through 30) block 31 lock configuration 010003 010002 010000 000003 000002 000001 000000 block 1 reserved for future implementation 00ffff 000004 block 0 reserved for future implementation reserved for future implementation block 1 lock configuration block 0 lock configuration device code manufacturer code 128 mbit 10 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc notes: 1. the lowest order address line is a0. 2. x selects the specific blocks lock configuration code. device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the two cycle "silicon id read" command is requested. (the command sequence is il- lustrated in table 3. during the "silicon id read" mode, manufacturer's code (mxic=c2h) can be read out by setting a0=vil and device identifier can be read out by setting a0=vih. to terminate the operation, it is necessary to write the read command. the "silicon id read" command is valid only when the wsm is off. table 3. mx26l12811mc silicon id codes and verify sector protect code type address (1) code (hex) q7 q6 q5 q4 q3 q2 q1 q0 manufacture code 00000 c2h 1 1 0 0 0 0 1 0 device code 00001 (00) 74h 0 1 1 1 0 1 0 0 block lock configuration x0002 (2) - block is unlocked dq0=0 - block is locked dq0=1 - reserved for future use dq1-7 read array command the device is in read array mode on initial device power up and after exit from power down, or by writing ffh to the command user interface. the read configuration reg- ister defaults to asynchronous read page mode. the de- vice remains enabled for reads until another command is written. 11 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc high z definition symbol when status notes busy? "1" "0" sr.7 no write state machine status ready busy 1 sr.6 yes reserved sr.5 yes erase and clear lock-bits error in block erasure or successful block 2 status clear lock-bits erase or clear lock-bits sr.4 yes program and set lock-bit error in setting lock-bit successful set block status lock bit sr.3 yes programming voltage low progr amming voltage programming voltage 3 status detected, operation ok aborted sr.2 yes reserved sr.1 yes device protect status block lock-bit detected, unlock 4 operation abort sr.0 yes reserved 5 table 4. status register definitions notes 1. check sts or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6-sr.0 are not driven while sr.7 = 0 2. if both sr.5 and sr.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se- quence was entered. 3. sr.3 does not provide a continuous programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, program, set block lock-bit, or clear block lock-bits com- mand sequences. 4. sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates the block lock-bits only after block erase, program, or lock-bit configuration command sequences. it informs the system, depend- ing on the attempted operation, if the block lock-bit is set. read the block lock configuration codes using the read identifier codes command to determine block lock-bit status. 5. sr.0 is reserved for future use and should be masked when polling the status register. high z definition symbol when status notes busy? "1" "0" xsr.7 no write buffer status write buffer available write buffer not available 1 xsr.6- yes reserved 2 xsr.0 table 5. extended status register definitions notes: 1. after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. 2. xsr.6-xsr.0 are reserved for future use and should be masked when polling the status register. 12 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc block erase command automated block erase is initiated by writing the block erase command of 20h followed by the confirm com- mand of d0h. an address within the block to be erased is required (erase changes all block data to ffh). block preconditioning, erase, and verify are handled in- ternally by the wsm (invisible to the system). the cpu can detect block erase completion by analyzing the out- put of status register bit sr.7. toggle oe, ce to update the status register. the cui remains in read status regis- ter mode until a new command is issued. write to buffer command to program the device, a write to buffer command is issue first. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the mtp device. first, the write to buffer setup command is issued along with the block address (see figure 3, write to buffer flowchart on page 15). after the com- mand is issued, the extended status register (xsr) can be read when ce is vil. xsr.7 indicates if the write buffer is available. if the buffer is available, the number of words/bytes to be program is written to the device. next, the start ad- dress is given along with the write buffer data. subse- quent writes provide additional device addresses and data, depending on the count. after the last buffer data is given, a write confirm command must be issued. the wsm beginning copy the buffer data to the mtp array. if an error occurs while writing, the device will stop writ- ing, and status register bit sr.4 will be set to a "1" to indicate a program failure. the internal wsm verify only detects errors for "1" that do not successfully program to "0" . if a program error is detected, the status register should be cleared. any time sr.4 and/or sr.5 is set, the device will not accept any more write to buffer com- mands. reliable buffered writes can only occur when vcc is valid. also, successful programming requires that the corresponding block lock-bit be reset. byte/word program commands byte/word program is executed by a two-command se- quence. the byte/word program setup command of 40h is written to the command interface, followed by a sec- ond write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr.7. successful byte/word programs require that the corre- sponding block lock-bit be cleared. if a byte/ word pro- gram is attempted when the corresponding block lock- bit is set, sr.1 and sr.4 will be set to "1". read status register command the status register is read after writing the read status register command of 70h to the command user inter- face. also, after starting the internal operation the de- vice is set to the read status register mode automati- cally. the contents of status register are latched on the later falling edge of oe or the first edge of ce that enables the device oe must be toggle to vih or the device must be disable before further reads to update the status reg- ister latch. clear status register command the erase status, program status, block status bits and protect status are set to "1" by the write state ma- chine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. 13 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc read configuration the device will support both asynchronous page mode and standard word/byte reads. no configuration is required. status register and identifier only support standard word/byte single read operations. table 6. read configuration register definition rm r r r r r r r 15(a15) 14 13 12 11 10 9 8 rr r r r r r r 76 5 4 3 2 1 0 notes rcr.15 = read mode (rm) read mode configuration effects reads from the mtp 0 = standard word/byte reads enabled (default) array. 1 = page-mode reads enabled status register, query, and identifier reads support standard word/byte read cycles. rcr.14-1= reserved for future these bits are reserved for future use. set these enhancements (r) bits to "0". 14 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc set block lock-bit commands this device provided the block lock-bits, to lock and unlock the individual block. to set the block lock-bit, the two cycle set block lock-bit command is requested. this command is invalid while the wsm is running or the device is suspended. writing the set block lock-bit com- mand of 60h followed by confirm command and an ap- propriate block address. after the command is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock- bit event by analyzing the sts pin output or status reg- ister bit sr.7. also, reliable operations occur only when vcc is valid. clear block lock-bits command all set block lock-bits can clear by the clear block lock- bits command. this command is invalid while the wsm is running or the device is suspended. to clear the block lock-bits, two cycle command is requested . the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing status register bit sr.7. if a clear block lock-bits operation is aborted due to vcc transitioning out of valid range, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. vcc--transitions block erase, program, and lock-bit configuration are not guaranteed if vcc falls outside of the specified operat- ing ranges. the cui latches commands issued by system software and is not altered by ce transitions, or wsm actions. its state is read array mode upon power-up, after exit from power-down mode, or after vcc transitions below vlko. 15 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 3. write to buffer flowchart start end command cycle - issue write-to-buffer command - address=any address in block - data=0xe8 check ready status - read status register command not required - perform read operation - read ready status on signal d7 write word count - address=any address in block - data=word count - valid range=0x0 thru 0x1f write buffer data - fill write buffer up to word count - address=address(es) within buffer range - data=data to be written no no no yes yes yes confirm cycle - issue confirm command - address=any address in block - data=0xd0 read status register see status register flowchart d7=1? write to buffer time-out ? any errors? error-handler user-defined routine 16 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 4. status register flowchart start sr7 = '1' sr2 = '1' sr4 = '1' sr3 = '1' sr1 = '1' yes yes yes no no no no sr6 = '1' yes no sr5 = '1' no no error command sequence yes yes yes error erase failure error program failure -setbywsm - reset by user - see clear status register command - set/reset by wsm sr4 = '1' yes no end command cycle - issue status register command - address = any device address - data = 0x70 erase suspend see suspend/resume flowchart program suspend see suspend/resume flowchart error v pen 18 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 6. block erase flowchart start write 20h to block address erase mtp block(s) completed full status check if desired write confirm d0h to block address read status register no yes sr.7=1 ? 19 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 7. set block lock-bit flowchart start write 60h, block address set lock-bit completed full status check if desired write 01h, block address read status register no yes sr.7=1 ? read status register data (see above) full status check procedure set lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes set lock-bit error no sr.4,5=1 ? sr.4=0 ? 20 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 8. clear lock-bit flowchart start write 60h set lock-bit completed full status check if desired write d0h read status register no yes sr.7=1 ? read status register data (see above) full status check procedure clear block lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes clear block lock-bits error no sr.4,5=1 ? sr.5=0 ? 21 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground voltage on any signal . . . . . . . . . . . . -2.0 v to 5.0 v output short circuit current (note 2) . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v and -0.2v on vcc signal. during transitions, this level may undershoot to -2.0v for periods < 20ns. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods < 20 ns. 2. output shorted < 1 second. no more than one output shorted at a time. stresses above those listed under "absolute maximum rat-ings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +3.0 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. 22 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc symbol parameter notes typ max unit t est conditions ili input leakage current 1 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd ilo output leakage current 10 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd 25 80 ua cmos inputs, vcc = vcc max, icc1 vcc standby current 1 device is disabled (see table 2) 0.71 2 ma ttl inputs, vcc=vcc max, device is disable (see table 2) cmos inputs, vcc=vcc max, vccq=vccq max 15 20 ma device is enabled (see table 2) icc3 vcc page mode read current 1 f=5mhz, iout=0ma cmos inputs, vcc=vcc max, vccq=vccq max 24 29 ma device is enabled (see table 2) f=33mhz, iout=0ma icc5 vcc program or set lock-bit 2 35 60 ma cmos inputs, vpen=vcc current 40 70 ma ttl inputs, vpen=vcc icc6 vcc block erase or clear 2 35 70 ma cmos inputs, vpen=vcc block lock-bits current 40 80 ma ttl inputs, vpen=vcc dc characteristics symbol parameter notes min max unit t est conditions vil input low voltage 2 -0.5 0.8 v vih input high voltage 2 2.0 vccq+0.5 v 0.4 v vccq=vccq2/3 min iol=2ma vol output low voltage 2 0.2 v vccq=vccq2/3 min iol=100ua 0.85 x v vccq=vccq min vccq ioh=-2.5ma voh output high voltage 2 vccq-0.2 v vccq=vccq min ioh=-100ua vlko vcc lockout voltage 3 2.2 v notes: 1. cmos inputs are either vcc 0.2 v or gnd 0.2 v. ttl inputs are either vil or vih . 2. sampled, not 100% tested. 3. block erases, programming, and lock-bit configurations are inhibited when vcc < vlko , and not guaranteed in the range between vlko (min) and vcc (min), and above vcc (max). 23 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 9. transient input/output reference waveform for vccq=3.0v-3.6v test points vccq/2 output note:ac test inputs are driven at vccq for a logic "1" and 0.0v for a logic "0". input timing being, and output timing ends, at vccq/2v (50% of vccq). input rise and fall times (10% tp 90%)<5ns. vccq 0.0 input vccq/2 figure 10. transient equivalent testing load circuit note: cl includes jig capacitance test configuration c l (pf) vccq = vcc = 3.0 v-3.6 v 30 device under test cl out rl=3.3k ohm 1.3v 1n914 24 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc versions vcc 3.0v-3.6v(3) (all units in ns unless otherwise noted) vccq 3.0v-3.6v(3) sym parameter notes min max tavav read/write cycle time 120 tavqv address to output delay 120 telqv cex to output delay 120 tglqv oe to no n-array output delay 2, 4 50 telqx cex to output in low z 5 0 tglqx oe to output in low z 5 0 tehqz cex high to output in high z 5 35 tghqz oe high to output in high z 5 15 toh output hold from address, cex, or oe 5 0 change, whichever occurs first tehel cex high to cex low 5 0 tapa page address access time 5, 6 25 tglqv oe to array output delay 4 25 ac characteristics --read-only operations (1,2) notes:cex low is defined as the first edge of ce that enables the device. cex high is defined at the first edge of ce that disables the device (see table 2). 1. see ac input/output reference waveforms for the maximum allowable input slew rate. 2. oe may be delayed up to t elqv -t glqv after the first edge of ce that enables the device (see table 2) without impact on t elqv . 3. see figures 10-11, transient input/output reference waveform for vccq = 3.0v - 3.6v, and transient equivalent testing load circuit for testing characteristics. 4. when reading the mtp array a faster tglqv (r15) applies. non-array reads refer to status register reads, query reads, or device identifier reads. 5. sampled, not 100% tested. 6. for devices configured to standard word/byte read mode, r14 (tapa) will equal r1 (tavqv). 25 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 11. ac waveform for both page-mode and standard word/byte read operations note: 1. ce x low is defined as the first edge of ce that enables the device. ce x high is defined at the first edge of ce that disables the device (see table 2). 2. for standard word/byte read operations, tapa will equal tavqv. 3. when reading the mtp array a faster tglqv applies. non-array reads refer to status register reads, query reads, or device identifier reads. tavqv tavav tapa tglqx telqx tehqz tehel tghqz toh telqv tglqv high z valid address valid address valid output valid output valid address valid address valid output valid output high z address (a22~a2) vih vil vih vil vih disable enable vil vih vil address (a1~a-1) cex[e] oe [g] vih vil we [w] vih vil vcc voh vol data[d/q] q0- q15 26 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc ac characteristics--write operations (1,2) versions valid for all speeds unit symbol parameter notes min max telwl (twlel ) cex (we) low to we(cex) going low 4 0 ns twp write pulse width 4 70 ns tdvwh (tdveh ) data setup to we(cex) going high 5 50 ns tavwh (taveh ) address setup to we(cex) going high 5 55 ns twheh (tehwh) cex (we) hold from we(cex) high 0 ns twhdx (tehdx) data hold from we(cex) high 0 ns twhax (tehax) address hold from we(cex) high 0 ns twph wr ite pulse width high 6 30 ns twhgl (tehgl) write recovery before read 7 35 ns twhqv5 (tehqv5) set lock-bit time 4 64 75/85 us twhqv6 (tehqv6) clear block lock-bits time 4 0.5 2 sec notes: cex low is defined as the first edge of ce that enables the device. cex high is defined at the first edge of ce that disables the device (see table 2). 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics-read-only operations. 2. a write operation can be initiated and terminated with either ce x or we. 3. sampled, not 100% tested. 4. write pulse width (twp) is defined from cex or we going low (whichever goes low last) to cex or we going high (whichever goes high first). hence, twp = twlwh = teleh = twleh = telwh. 5. refer to table 4 for valid a in and d in for block erase, program, or lock-bit configuration. 6. write pulse width high (t wph) is defined from cex or we going high (whichever goes high first) to cex or we going low (whichever goes low first). hence, twph = twhwl = tehel = twhel = tehwl . 7. for array access, tavqv is required in addition to twhgl for any accesses after a write. 27 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc figure 12. ac waveform for write operations notes: 1. cex low is defined as the first edge of ce that enables the device. cex high is defined at the first edge of ce that disables the device (see table 1). a. vcc power-up and standby. b. write block erase, write buffer, or program setup. c. write block erase or write buffer confirm, or valid address and data. d. automated erase delay. e. read status register or query data. f. write read array command. twph tavwh (taveh) twp twhdx (tehdx) twheh (tehwh) twhax (tehax) telwl (twlel) tdvwh (tdveh) twhgl (tehgl) din address (a) ab cd e f vih vil oe vih vil vih disable enable vil cex,(we)[e(w)] vih disable enable vil we,(cex)[w(e)] vih vil data[d/q] din ain ain din valid srd 28 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc limits parameter min. typ.(2) max. units block erase time 2.0 15.0 sec write buffer byte program time 218 900 us (time to program 32 bytes/16 words) byte program time (using word/byte program command) 210 900 us block program time (using write to buffer command) 0.8 2.4 sec block erase/program cycles 10 cycles erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,3.3v. additionally programming typically assume checkerboard pattern. parameter test conditions min unit minimum pattern data retention time 150 10 years 125 20 years data retention min. max. input voltage with respect to gnd on oe -1.0v 12.5v input voltage with respect to gnd on all power pins, address pins, ce and we -1.0v 2 vccmax input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf capacitance ta=0 c to 70 c, vcc=3.0v~3.6v notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz 29 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc ordering information plastic package part no. access time package type (ns) MX26L12811MC-12 120/25 44-sop 30 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc package information 31 p/n:pm0990 rev. 1.0, oct. 29, 2003 mx26l12811mc revision history revision no. description page date 1.0 1. removed "advanced information" from title p1 oct/29/2003 2. typing error p12 mx26l12811mc m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. |
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